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  • Hey all, just changed over the backend after 15 years I figured time to give it a bit of an update, its probably gonna be a bit weird for most of you and i am sure there is a few bugs to work out but it should kinda work the same as before... hopefully :)

iMac Pro

Antony Newman said:
Most PC manufacturers do not have the requisite acoustic experience to optimise internal space for high airflow without psychoacousticlly annoying wind noise. The 'slot' exit port at the bottom of the monitor is a great step in minimising noise. If forcing of air though (what looks like an aperiodic cavity formed by) the fins of the heatsink - shifts enough air, they can provide almost any desired cooling.
Click to expand...

I'm pretty sure from the animation they showed in their presentation the exhaust is at the top and not the bottom. The bottom slot would be an intake. Since heat rises that would make the most sense. Also, if air was exhausting out of the bottom there would be more noise made from that air hitting the hard surface of the desk or table or even the stand.
 
The air gets pulled in from the bottom intake slots by the sooper dooper fans, coming through both directed channels through the chassis behind the display's edges and over the system boards, then directed into the heatsink in the middle of the board, and then forcibly pooped out the rear vent to the sides of the body, by the airflow pressure. In short, the fans are the one and only cooling measure and if they go bad or get reduced efficiency, you're screwed. You'll also want to pay attention to the orientation of the body, as it will affect cooling efficiency and airflow, hence why the unit is shown at an angle, instead of straight on.

https://arstechnica.com/apple/2017/06/heres-hoping-the-imac-pro-learns-from-the-mac-pros-mistakes/
 
The problem with AMD stitching together the multiple dies to gain cores is problematic. Bandwidth is actually quite restricted and it relies on PCIe interconnects for much of the transactions between each sub-CPU or bank of cores. While I agree with a lot of what Antony is pointing out for AMD, he's ignoring a lot of what Intel has in the pipeline. In the end though this resurgence from AMD is a great thing all around for everyone. It's forcing Intel to push forward at a faster pace and opening up more options for consumers.

My biggest issue with the latest offerings from AMD is that their CPU products are performing as typical and in line with their GPU offerings. They look amazing on paper, but real world numbers are more one the disappointing side. My 8-core Ryzen here is interesting, but can't hold up to my 2 year old 8-core Intel build. Sad. Of course there is a pretty large price disparity between the two, but still Ryzen just isn't cutting it against the top Intel offerings. The 18-core ThreadRipper is suffering from much of the same from what I'm seeing in benchmarks from OEMs.

I'd love to see AMD or someone, anyone, show up with something that stomps all over Intel, but it's just not happening. And AMD is fighting an uphill battle with their CPU products -- one because the performance per core is lacking and that's a big issue in markets where power counts. And in the general corporate world, Intel is almost mandatory across the board in terms of what these corporate purchase departments are willing to buy or are allowed to buy. AMD making inroads into these markets is going to be a real challenge.

OTOH, if AMD can beat Intel to the punch with 32 and 64 core offerings, they may just have a chance to really gain some serious ground. We shall see. They're talking a lot about higher density and fab processes up to 7nm. Have yet to see lab data and fully functional proof of concept.

Intel is not in much of a predicament. Much of their upcoming tech has been researched and sidelined for scheduled roll-out to maximize profits. Intel will simply adapt and sale prices appropriately at this point. AMD is playing catch up and they are really going to need to go for it and drop a serious bomb if they want to shake things up and keep Intel from simply matching step and keeping 1~20% better at 50% higher cost with name recognition. If they could drop a 64-core CPU with turbo speeds capable of at least 4 cores at 4.5GHz, and ability to run all 64 cores at 2.8GHz or better, they would have a winner. Better drop that by the end of 2018 to bet Intel to the punch. 100+ accessible PCIe lanes would be a bonus too. Intel is struggling when it comes to offering enough PCIe bandwidth and this is one area where I think AMD has a chance to capture a big part of the professional market.
 
Antony Newman said:
Wayne.

CPU Frequency
+) For current Intel 10nm / 14nm FinFet transistor designs - increasing Ghz from (eg) 4 - 5 Ghz can double the power consumed.
+) 4 cores at 4 Ghz is often preferable to 2 core at 5 Ghz, or 1 core at 6 GHz
+) If you had a monster sized SoC - it is possible to architect it so that 'duff' / 'bad' CPUs are clocked slower / switched off.
+) Intel keeps the 'best' ones -> sells them to the Data Centre
+) For the 'worst ones' -> they might be core disabled -> have the Memory Channels HALVED and sold as 'Consumer'

Multi SoC
+) Intercore (on chip) latency does have an impact, as does (usually a few times larger) inter (close proximity) Soc latency on performance.
+) However - it is the Bandwidth that I believe is the upper limit on multi CPUs working effectively together.
+) As the number of cores grows - the MEMORY bandwidth starts bottlenecking (if there is information Flowing through the system).
+) Intel is a quandary right now ... as to compete with AMD's CONSUMER chip, they might have to 'Allow' more memory channels.
+) The AMD fabric (on GF 14nm) scales almost linearly to 64 cores (intercore & intersoc - excluding memory access)

AMD_Ryzen_Mark_Papermaster_Final-page-013.jpg


AMD
+) Didn't have the resources or technology to have separate Data Centre & Consumer products. That may change when they release EPYC or (7nm) STARSHIP.
+) Zen / Ryzen / Naples / Threadripper : My understanding is that at 14nm - they will all use the 8 x CPU core bits of 'lego' to make 8,16 or 32 core single socket chip. The 128 x PCIe 3 per 8 x CPU SoC is Mostly used to provide inter-soc / or CPU <-> GPU comms.
+) If by some magic AMD implement PCIe 5 on 7nm (I would amazed if they did) - 2019 could well quadruple the scalability of their fabric.

AJ
Click to expand...

Thanks Antony.

5ghz is very old technology. CPU's are designed towards lower power and higher multicore since then. The issue I'm ask the higher clocked cores for, is simply some tasks, and some apps unnecessarily, are optimised for one or two core, so more cores are useless. If we could have specific workstation custom high GHz designs on a few cores, they could do most of the heavy lifting, maybe one more core operating low speed to look after the system, and the rest powered down, when running these apps. So, I expect two cores running at the thermal limits on a cryo setup might reach 10ghz, what ever process technology is needed for that, and certain users will be appreciative. As for running the all the cores together, they would dynamically clock down to maintain the power envelope as normal. It is just for non parrallelable apps, even running one fire fastest. You see it is a special use compromise. Also, I'm sorry, I haven't been thinking to explain to people, that processes and designs are tailored for speed or low power. So, just because one design responds a certain way to an increase doesn't mean another design won't do better. It also would be a chance to address the interlink sub system. So I'm not necessarily talking about today's Intel or AMD designs, but what they can do in the future.

Of course, if post application makers would simply design their programs to better scale across cores, we personally in the video industry would have less need for higher GHz cores, but they don't.


Now, this pcie on chip communications thing, I'll admit. Is dismal. I'll explain it for others here. Converting to phase based signalling introduces a performance penalty, but off chip higher speeds and note parallel lines is impractical, though I have been working on design proposals to reduce this performance penalty (which Jeff might he interested in assuming he is still reading. Significantly big stuff). When you go off chip the signal has to be changed for the external interface, further reducing performance (pays to hang around leading microprocessor designer). However, when you stitch together a multiple chip die, you should be almost able to produce a straight connection with little performance loss unit to unit on the chip compared to going external pcie. So, it should not be the same, and I would love to know what sort of pcie it is, and its performance characteristics (if they are better than external pcie). However, what a shame not to use a propped on chip interface. Even if you are stitching together multi core chips with external pcie interfaces (what happened to the fast external memory interfaces) you could design the connections to have a bi-passable pcie section, allowing more direct connection (though, now you have less pins and it may break the performance by degrading the pcie signal/line characteristics, to substitute an intra chip speed like connection). I suppose those might have been a reason they choose to go pcie, to maintain the sellability of these tiles as individual consumer CPU's. However, it occurs to me if they mount them on something, that something could have circuits linking to a second set of intrachip like connections, bypassing (possibly before the pcie section, exposing the parallel lines going into the pcie section). I imagine this right hand turn might introduce a bit of performance penalty, but light he somethingnAMD has not considered. But frankly, they really need optical links off the tiles anyway, which could be better, providing more opportunity for edge links, though an optical link built into what the tiles are on is feasible. Now, in either case, whatever they are mounted on can be made cgeaoly at low compkexcity and defect, and easily discarded if defective, with the tiles themselves being the expensive bit. But, looking at the sized of outputs possible off the edge of chips, you might just he able to squeezed the parallel lines in between the pcie lines off the edge (I am saying but and weld/seal here). So, there are options to present a fast multiple tiled chip (frankly, in my own low powered design proposals I want to put memory and comms in the substrate the tile is mounted on (not much heat issues in low energy, and you have techniques to reach lines to the substrate). So, what is AMD doing?


Now, as for performance penalty of using PCIe, not so much if application developers design their application workflows for it. Unfortunately there has been an issue with developers not dong this, and optimising for whatever Intel architecture. Now, if AMD can maintain mainly one CPU scalable tiled architecture, then performance application developers would gave just one amd performance architecture to optimise for, which AMD really needs in order to make optimisation support easier for their product. All last years and before products are irrelevant marketing wise, to optimise more for. But and has to work towards the best solution across chips, which probably means one more long teem interconnect to optimise for before possibly going optical.

Mike Halper said:
I'm pretty sure from the animation they showed in their presentation the exhaust is at the top and not the bottom. The bottom slot would be an intake. Since heat rises that would make the most sense. Also, if air was exhausting out of the bottom there would be more noise made from that air hitting the hard surface of the desk or table or even the stand.
Click to expand...

Jeff Kilgroe said:
The problem with AMD stitching together the multiple dies to gain cores is problematic. Bandwidth is actually quite restricted and it relies on PCIe interconnects for much of the transactions between each sub-CPU or bank of cores. While I agree with a lot of what Antony is pointing out for AMD, he's ignoring a lot of what Intel has in the pipeline. In the end though this resurgence from AMD is a great thing all around for everyone. It's forcing Intel to push forward at a faster pace and opening up more options for consumers.

..

I'd love to see AMD or someone, anyone, show up with something that stomps all over Intel, but it's just not happening. And AMD is fighting an uphill battle with their CPU products -- one because the performance per core is lacking and that's a big issue in markets where power counts.
..

AMD is playing catch up and they are really going to need to go for it and drop a serious bomb if they want to shake things up and keep Intel from simply matching step and keeping 1~20% better at 50% higher cost with name recognition. If they could drop a 64-core CPU with turbo speeds capable of at least 4 cores at 4.5GHz, and ability to run all 64 cores at 2.8GHz or better, they would have a winner. Better drop that by the end of 2018 to bet Intel to the punch. 100+ accessible PCIe lanes would be a bonus too. Intel is struggling when it comes to offering enough PCIe bandwidth and this is one area where I think AMD has a chance to capture a big part of the professional market.
Click to expand...

As much as I didn't like it, I think they need to consider going back to putting high end CPU's on daughter cards that vertically plug into an extremely wide main board slot. The advantages are that a continuous segmented slot of less pins, is mainly pcie and maybe memory which can be on the cards, and multiple cards can fit in one line, and even with a new mainboard form factor standard, be thermally ported by cooler fans straight out the top of the case. We gave reached thermal limits, and short term chip limits coming, it is time to redesign the cases to handle multiple kW CPU's and gpu's. I'm also available to attempt 100ghz plus processor designs. There is a lot that can be done, even to mostly eliminate leakage (have has some relates thoughts for a while).
 
Wayne,

HIVE
DARPA in my opinion demonstrate an architecture that scales very well for graphical analytics workloads
http://www.darpa.mil/attachments/HIVE_Proposers_Day_PM_Briefing.pdf

Replacement of Copper with optical connectors
+) IBM Research solved many of the big puzzles in 2010.
+) For mass adoption - it comes down to 'when will the optical solution be cheaper'.
+) They (IBM) are currently trying to 'shine a light' on their current 69Gb/s 100m error rate 1 in 10^12.
It is coming ... but will hit the rack space first.

Others feedback on the ImacPro air intake : Thanks.
+) My guess, is that the reason that Apple didn't want anyone touching the iMacPro .... was that they'd burn their fingers!

AJ
 
More new stuff to learn :)

So, is Hive better for video processing or graphics. I'm sorry, I'm not going get to study it at the moment.

I avoid red getting into the optical stuff, because to make it consumer we have been waiting on Intel's silicon laser technology, which AMD doesn't have. However, even long haul WAN links have been doing TB/s. What we need is to look at a spectrum of frequencies at once. We get the chance to communicate hundreds of bits )as happens on chip) to hundreds of frequencies, but that us perhaps a step further than they are attempting, but I can see a possibility for a structure that passively generates the separate frequencies from an input frequency, but that maybe affected by thermal changes, so then you change materials to reduce expansion, which means likely, printing or stick it on. So, the best solution might he to stick it in the substrate the tikes are on, which contain linking optics, but allows the structure to be linked to the laser on chip and bit lines. But going further, the substrate the tiles are assembled from could have the optical laser and network. If so, the network could be pumped by a laser device integrated or not into this substrate, the optional to use (depending on if in a single or tiled use) parallel lines would then connect to the tileing substrate (notice the different language is because things can be done chip flipped or not flipped). That is an option for AMD, and depending on the optics high end performance or not. Now, in their super computer chip, optical might he very suitable as it can connect to an interchip optical network. So, there are cheap higher performance alternatives to pcie and full performance options. I actually have techniques that would give much much better links on mass parallel chips then existing techniques, resulting is possible multiple times speedups for high end workstation workloads, or others.

Now a question, and I know they use different chip processes, but when will we see a workstation chip with full AMD GPU and highest speed CPU in one package. Again, a long maybe wide socket or card. It could still be tiled. But, the issue is to provide very high shared memory and communications links between the CPU GPU and memory. So, let's say 64 cores CPU with x percentage of highest speed cores connected to two or more highest end AMD GPU. So, 2+ highest speed tiles could be distributed for thermal distribution to run some cores at highest speed exclusively. The interesting thing, so can you distribute these tiles around to even out the GPU thermal. Also tiled can be a lot of memory, highest speed memory on the fastest version. This could be further used to even out thermals. In a lot of cases a lot of the circuitry is unneeded, including a lot of memory, absorbing surrounding heat, increasing highest running thermals of the ones working. This suites workloads that are limited in their parallel distribution that require maximum performance. In such a case, say 90% of the circuit is unused. This is very viable. But nvidia us the one concentrating on pursuing turning up or down sub circuits as they are used or not dynamically during use. This is the ultimate pursuite of this. Now, that means you might have a 20cm wide cooler (again, new form factors). Now, going a step further, more effucent processing tiles can be put in then gpu's. This might mean a 10x performance speed up for non 3D and graphic operations by moving the space used by some gpu's to such an array that maybe based on memory circuit based processing arrays (very efficient) where the processing sections are designed on memory chip processes. So, past one or two gpu's to do graphics, there is little need for more on a lot of workloads, as many could be done by CPU or dedicated processing array which can be a mix of fastest speed fires with a mass array. At the same time, the space of the package shrinks because many workflows simply don't require what you can fit in 20cm titled package. So, a quarter the space maybe used. In normal computing, except games (which may want a two or four GPU version), an apu is probably fine, as we see in i3 only systems, as what do you need for a office and web. For servers, a different tile configuration is needed, for ai another. However, this makes things affordable for AMD, as two versions of a discrete desktop CPU designs only are required, and you can.mixband match according to purpose. This means you are voluming the lower volume tiles other less wafers, instead of packaging into large dies with CPU's, allowing greater volumes of the CPU itself. Every component receives some cost advantage, except things like apu's, where cpu and gpu are always closely together in volume. The titled package is a lot of the main board, and a little extension of the design it can become a main board (mainly card slots and sockets plane).

So, you can see an opportunity to greatly outstrips high end workstation designs (most here don't get hold of and your local computer store usually can't make anything near) at half the cost.

Now, for us, we could say a $1000-2000 computer that processes more than 8kp60 16 bit redcode, as we only require a portion of this power. A high efficiency processing array would act more like a highest end red rocket at a tenth the price by AMD or Intel. Actually, it is a good opportunity for Red to see if the underlying processing technology (I assume is the European one I'm thinking of) is suitable to sell to AMD to tile into a workstation ruled package. Once somebody has a mid range graphics card, a lot of non graphic workstation flows can be done by a non gpu processing array. Just one series of workstation package is possibly needed, and if you need extra 3D, you just add an extra GPU card.


Antony, iMac Pro burning the fingers. Is that with the 18 cores? :)
 
Antony and Jeff,

Antony I just realised you were talking inter socket PCI e, which is understandable. But Jeff, is it true they are using pcie between the tiles for interconnect? When I heard you say it, I thought it was just a convenient choice AMD made, but not the best performance.
 
Scheduled for 2017:
But In don't know how this relates to the under 200w, at least 10 teraflop compute performance chip, or the mobile apu out this year.

https://www.top500.org/news/pondering-amds-ambitions-for-high-performance-apus/#rating-306
https://www.nextplatform.com/2017/02/28/amd-researchers-eye-apus-exascale/
The chip would combine 16 Zen cores (up to two threads per core) with a large “Greenland” (now “Vega 10”) GPU. The processor would be hooked up to a 16 GB HBM device via a silicon interposer, and deliver 512 GB/second of memory bandwidth to the APU compute units. Four channels of DDR4 memory would also be included, supporting a maximum capacity of 1 TB. Although those specs clearly point it toward HPC and other high-end server work, such a design could be scaled down to AMD’s desktop and laptop markets as well.
Click to expand...

28 core Xeon:
Interesting the comparison between the 28 core Xeon, current faster 24 core Xeon and the 18 core i9.

https://hothardware.com/news/intel-...um-8176-server-cpu-rocks-cinebench-benchmarks
 
Yes it’s true about the PCIe interconnects between AMD CPU core modules. This allows them a to utilize a LEGO building block approach to CPU design. Simplifies many aspects, but the performance takes a serious hit and degrades rapidly as the core count scales up. It’s going to be interesting to see how the CPU market plays out over the next couple years, but what I’m hoping for from AMD is they will help drive down costs on the consumer / prosumer end of things. They’re not going to catch up to or beat Intel. Intel is at 56 cores at the moment for their top Xeon offering (112 threads). It can operate two cores at 3.8GHz (turbo) and all cores at 1.6GHz. Currently dual CPU operation is available with this core count. The 4-way and 8-way variant arrives in August or September. This is a monster CPU for virtualization and cloud apps. Not so great for broad compute or render tasks, workstation use, etc.. The 18-core v5 Xeon, which should be the one that makes it into the iMac Pro, is also launching this fall. That seems to be the current limit of where practical GHz speeds for desktop workstations come to an end. Looks like it will come in 150W and 190W TDP flavors and I’m betting on the 150W version in the iMac Pro. This also aligns with the top 8 core offering is at 150W and the second best 10 core offering is also at 150W. The 10 and 18 core have the same turbo frequency, but the 18 core gives us another 8 cores operational at only a 400MHz penalty. The new hot-rod 8-core 150W Xeon gives us 8 cores at 3.8GHz with turbo at 4.5GHz. And Apple’s little teaser is saying 4.5.GHz turbo. So I think that’s another good indicator they’re going with the v5. That and timing waiting for Vega.

The new 18 core Xeon and i9 18 core CPU are both going to outperform the AMD 18 core ThreadRipper. No real question about that. Unfortunately we’re going to be paying a steep premium for that advantage.

I’m curious to see how well that 18 core i9 will overclock. Not expecting huge gains myself as the current 10 core units have been mostly unreliable and lackluster in that area with lots of incidents of internal heat spikes under sustained load.
 
So, my design ideas I was speaking to you guys about, and the bits I was specifically speaking to you about, would really help this tiled design's interconnect data rate?
 
Now, that is more interesting then the entire Apple lineup Frank. It would need at least 2160p height though, and a physical height of at least a 27 inch screen (40+ preferably). Two gtx 1080 ti cards, an top i9 or AMD thread ripper at least.

Here is something else, and they also do some video editing:

http://www.digitalstorm.com/aventum-3.asp?workstation=1
 
What we need to do, is find out who actually makes that All In One, and see if they have ant.more suitable models for us.

Anybody near one of these units to try to find OEM markings?
 
Wayne Morellini said:
Here is something else, and they also do some video editing:

http://www.digitalstorm.com/aventum-3.asp?workstation=1
Click to expand...

Since I left Apple - around 2001 - I build my own Workstations. Can't beat the price/performance - bang/buck ratio.
Not to mention future upgrades and flexibility.

With a well build desktop, IMHO water cooling doesn't have any benefit - I never run into a heat problem.
But if you don't have the nerve (or time), to dig in all you have to know, to build a fast and solid workstation, builders like DigitalStorm offer way more, than anything you can buy of the shelf.
 
Frank, I've interested in finding some good case design resources to build case enclosure designs. Do you know any sites that do that?

I'm pretty sure something better than Dan's case is possible.

I'm interested, is a 4 card gtx-1080 ti system really useful compared to a 2 card system, or will work with red code or resolve not really benefit?
 
It's an issue though. It makes me wonder how high end Volta or Vega will do instead if 4 cards gtx.

Still, how many cores and cards scale how, us what Red should be publishing for Redcode. A 2 core 2ghz chip could handle 2kp24 cineform in 2005, and as redcode uses cineform technology. Surely that might give some indication (though not as simple). So, that's 32 cores at 8kp24 at 2GHz, 64 cores at 8kp50. Which is yikes. And will it ever scale that well. So, what sort of GPU acceleration is needed?

So, next question is, through open cl and compute api, are there any FPGA, or cheap processing array cards alternative to redrocket? That might end up one card instead of $2000 extra GPU and CPU.
 
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