New MacPro predictions? Hopes? Fears?

[Wayne Morellini]

http://www.tomshardware.com/news/gen-z-interconnect-storage-class-memory,32844.html

 

[Jarek Zabczynski]

From Jarred. :smile:

What else he tell you! :drool:

 

[Peter Majtan]

...But with my design you could get rid of the rack and vertically mount on the desk...

Wayne - this I guess is where we disagree. With the exception of xServe - all Apple workstations were meant for desk (or near/under desk) location. There are several companies manufacturing rack-mount kits for all these workstations - that alone should tell you something. Virtually every single person I have spoken to over the last few years regarding even 4K workflow (never mind 8K) - and we are talking hundreds of professionals similar to me - they all do not want the workstation on their desks, or even anywhere near them. It needs to be stacked away in a rack inside chilled server room. The amount of cooling required for this processing will not only mess with the noise, but actually the temperature in your suite as well... ;o)

:sifone: Peter

 

[Wayne Morellini]

I understand Peter.

I realised something, my writing wasn't clear, I meant the blades stand up on their sides (vertically). I don't mind it being on the back of the desk where I can access drives etc. Some quiet cooling solution. But some separate chilled room is a fantasy at my level, even a chilled cabinet Peter (like to keep an eye and ear on what is happening traditionally, for hackers (here it doesn't matter, just force of habit, in matter fact, I want a hardware wired blinking colored lights on everything (anybody know of anything you can loop around a cable or inbetween cables and sockets?))).

 

[Antony Newman]

Ooo ... grapevine looks like Apple are beefing up their on chip GPU abilities.

John Metalfe is moving into the mothership...

AJ

 

[Wayne Morellini]

Antony, have a look at this:

http://www.eetimes.com/document.asp?doc_id=1325714

You seem to be stuck on Apple's next Arm, but Nvidias next Arm is coming. I imagine Nvidia is also aiming to use Arm for the desktop and high performance computing, and that might have been one of the eventual aims. However, RiscV offers a good path.

A lot sexier then my old design, but not as good:

http://csglobe.com/glass-orb-future-solar-energy/

Another one, below. We have a guy in Australia that forecast 8000 liters a day on his wind design. I came up with an alternative years ago, with much higher capacity than either of these, with electricity and air-conditioning.

http://www.computerworld.com/articl...or-can-produce-energy-clean-water-and-ac.html

I have been eating to contact IBM about another project.

 

[Antony Newman]

Thanks for the links Wayne.

There are two other companies that introduced 64 core ARMs SOCs one Chinese that is very quiet about their accomplishment, and a South Korean one that I believe is testing tape outs. The Chinese chips are destined for Supers, the South Korean chips seems more suited to high bandwidth uncorrelared processing (like a network device).

There are both impressive steps in the scaling direction of CPU power, and will eventually democratise multicore use in High Performance PCs.

The reason that I am 'betting ARM' is because mobile companies are pushing forward at a heck of a rate, that investment funds are rallying around IoT (e.g. Saudi Arabia), that ARM are architecting open solutions, and SoftBank are working feverishly to accelerate ARM into the server and IoT world.

NVIDIA emulated cores are fascinating, my gut feeling is that NVIDIA will be able to rapidally iterate a design that allows the feeding of the GPUs. But that their design uses more transistors that is absolutely needed, and is not therefore an optimal if you want a large number of ARM cores.

TSMC

I think that TSMC is a quintessential piece of the puzzle, that have dealt themselves an enviable hand.

TSMC bet on the right horses. They involve ARM (and therefore Cadence) in proving and optimise foundry design rules - on their next but one process. They bent over backwards to keep Apple happy, and they have thrown everything they have got into being part of what comes 'after phones'.

TSMC think that at the end of 2017 they will be taping out design for the High Perfromamce Computer world, and they think that HPC will be the Next differentiating technology (along with IoT).

TSMC think their 7nm process + Some unknown design + lots of cores in 2017 = Impressive new HPC designs.

I don't think the design will be Alpha, MIPS, RISCV, Power, Phi, Xeon, x86, Sparc .... I am predicting it will be ARM based, it will scale up to dizzy heights of cores, efficiently process HPC loads that work in a coherent mesh with data cache + CPU avaibale at each node.

ARM have a mesh and already have 'off the shelf' cores if a company does not have their own designs. HOWEVER, Apples A10x seems to have reached mid level XEON cores in their performance. When Apple release their mobile core on TSMC 7nm - I would expect to leapfrog Intel.

With Apples poaching of Imagination Technologies CTO, I think Intel will find its profit margin will finally go down a notch as they are forced to reduce the Total Cost of Ownership of the x86 offerings, branch out into vision, drones, and mobile comms.

My far fetched prediction is the A11x core is going to be a HPC ready offering.

AJ

 

[Wayne Morellini]

We can hope. But MIPS is royslity free. Imagination is pushing their MIPS design.

TSMC is ahead of schedule on their next node process I here. 7nm is the limit for silicon before it just gets hotter as you shrink. Heat is the limiting factir on dealing with HPC under this regime. Swapping from expensive Arm (and in circuit size) to something smaller/lower power gives better performance. RiscV is a way to increase performance in 7nm silicon bottleneck space.

Nvidia, their Arm runs faster cooler, so you can pack more together. They shouldn't be discounted, but they are using RiscV now in unrelated application, so hopefully they will move main stream like others are planning. What's his name with.the $99 credit card sized "super computer" (which seems to be nothing compared to the Nvidia credit card sized TX1 Jetson board) is going to use RISCV in his next design. But a vital question then arises:

OpennCL is designed to allow a program to use all resources, not single ones like cuda. So you can added future new hardware and have current code access that performance. So, something like riscV controlled array of new "supercomputing" chips could be implemented and attached to a PC and used. However, a few issues with Open CL aside. How come people are not concentrating on it?

About Nvidua emulation. They are pretty savy in reducing power consumption, before most manufacturers I would think. Do you have figures that prove their emulated Arm uses more transistors then equivalent Arms in performance or features?

I wanted to get Nvidia interested in the technology of the firmer group I was around years ago. They have the record for low energy by far, and an advanced high perfirmance design they have had up for years. Nothing like these pitiful old style processors, including even RiscV (which is just a good standardisation compromise that can benefit the industry, hence my support). My original thought was as a GP-GPU implementation. I'm yet to finish my own design mechanism, as I had an idea how to structure everything for all the different calculation scenarios then lost it before I could put it down latter.

I remember years ago people mocked that I thought I could use a design to emulate an ARM, Android or x86 more efficiently than the original. But since them such emulated chips have become a reality, and indeed in the 80's/90's there were other x86 efforts. There are ways you can get a practical benefit from emulation on a much higher performance density processor, particularly in this heat constrained environment. I still haven't given up hope of running my design at 10-50ghz on a present node process though (maybe with a minor modification) (that tends to be the sexy figures people look for) but in reality I can fit far more chips in on 2-5ghz. Would be interesting to have a 3D 4k tranisistor design at the middle of cooling system and see how fast you could run it above 100Ghz. It is pointless though, 4k T would have to be a special design as a standalone processor that does much. However, I would have to sit down and think about how michnI could archieve in the present design in 4k, certainly in the future designs that are not transistor based I could get note functionality. But that's not on st the moment with my brain health.

 

[Wayne Morellini]

I am just realising a new form of quantum computing that is practical from that dream I had. Maybe hundreds of times more dense than the atom lattice circuit designs I'm thinking of doing. How dense, I don't know. I'm just contemplating how to apply this to the subatomic level, well past optical. OK, now I'm applying it to the planck level, this is the most amazing thing, and well and truly past anything I've come up with before, which was itself well and truly past anything before and on the planck scale, by shifting the way its done. The amplification stages to get it to the real world is a challenge. Hmm, you can make an artificial neural brain this way. It can be started with today's technology, and my other proposals can get down to the planck length. There is no other method that can be better. This is now the most important post in computing history.

 

[Wayne Morellini]

Nope, just realised a limitation that may reduce the planck level performance, but may not, we don't know enough about the planck level. But it is still likely ahead of my previous proposal for planck level.

 

[Antony Newman]

Dynamic compilation has to trade latency with code parallelism optimisations.

If you have code that does not change - you can spend thousands of hours compiling at a lower (microcode) level and get a create a more performant system.

However, writing general code presents corner cases which causes this solution to be less performant than an off-the shelf ARM core.

My understanding, is that this is reason that Nvida had to bolt on 2 x ARM cores (old ones at that), onto each Denver core.

Answering your question would be more along the lines of the following:
+) What is smaller : 2 x ARM cores vs 1 x Denver + 2 x A57 ARM cores.

You may be aware of the two teams that design the ARM cores .... the French team designed the A73. It the smallest ARM v8 by area ARM have ever desgned. (The 10nm A73 is 0.65 mm^2).

The A73 represents a step DOWN in IPC vs the A72 (French team's chips have lower latency, smaller pipeline, less area, lower IPC).

However, Apple's Hurricane is (I presume) ahead of all other ARM chips, and somewhere in the land of Intel (we'll find out by 2017 Q1).
To keep chips nice an cool, lower GHz + High IPC is a pretty good recipe for low TDP (although I admit I am not much of cook).

-----

Slight change of subject :

I wonder if the next Mac Pro will incorporate a Speaker & directional 'Siri' Microphones ... and will be 'always on'...

AJ

<snip>About Nvidua emulation. They are pretty savy in reducing power consumption, before most manufacturers I would think. Do you have figures that prove their emulated Arm uses more transistors then equivalent Arms in performance or features?.

 

[Wayne Morellini]

Thanks Antony.

Ha, ha, about the microphone. In that case buy a HP before somebody threatens to expose to your wife how much you swear in front of the computer. Seriously that would be bad and very compromising. People could spy on you for commercial reasons from anything with a speakers, or some mechanism that varies depending on vibration, even your hard disks or router.

However, a very good mechanism that produces pure sound that I wanted to use from the 80's was when they crossed two beams of ultra sound over and the difference in frequency produced a pure sound wave of that frequency. Would lobe to see that, would be very cool and very compact in a MAC pro with mid space placement. Of course I imagine the sound is very spread, but just at the end of a portal in a case should control it. Don't ask me about microphones though.

 

[Wayne Morellini]

Ok. There is a lot of talk about a new Nvidia shield TV at the moment. But only parker is mentioned, and except for those denver 2 cores being said to be a big advancement, there is not much advancement expected in performance (the Maxwell GPU used in the TX1 is said to be a half step design between maxel and pascal) however some good extra features for virtualisation etc are included. It maybe that the new shield is just a cheaper revision.

The Xavier is interesting. 8 custom cores, equivalent to 2 parkers (according to some AI metric, which means??) on 16nm again, only 20 watts TDP, Volta GPU. Sounds strange that in 2018 they will still be using 16nm for increased performance.

http://www.anandtech.com/show/10714/nvidia-teases-xavier-a-highperformance-arm-soc

 

[Antony Newman]

Maybe there is scope for an 'always on' device like an Alexa:

+) A large hollow object (that could house electronics) and have space to compress & rarefy.
+) Always on = creepy but more useful assistant & No boot time.

+) Directional sound output = Possible, but I think a B&O style inverse wave guide is all that would be needed (to send midrange out horizontally)
+) Vibration cancellation was pioneered by Laurie Finchman during the Ref107 design.
+) Lobing issues I don't think would be an issue with a single driver (or if needed line array)

(multiple) Microphones : This is an area that companies like Sennheiser seem to have mastered with the Momentum's. Amazon's echo may be the Gold standard to beat.

Nvidia : There is lot of money to be made in AI 'training' , 'learning' and automotive.
My understanding is that Nvidia is shunning the multitude of other companies with interconnection standards (much like Intel does), as it is not in their (financial) interest.

Nvidia does not want CCIX (ie the ability for the GPU NOT to be the centre of the universe).
As impressed as I am by their innovation - I hope they do a u-turn here.

AJ

EDIT : Correnction Re : Nvidia. I think after the DOE got Nvidia & IBM Woking together with NVLink & Volta & Power 9, Nvidia have joined the OpenCAPI standard - which like CCIX will help break the Intel stranglehold. OpenCAPI is a good standard, but will need someone who actually fabricates SOCs to build them.

 

[Wayne Morellini]

Ok, now the issues you mention with the Denver. The Denver 2 has a new routine and improved performance. I can't answer for what they have done, but can tell you what I would do (from an hour ago, so I'm forgetting by now).

Firstly, there is a lot of static code in their firmware that can be setup and compiled to be conducive to the custom CPU. But why bother doing that, when you can compile native anyway, and bypass the ARM portion. Not much an issue except to hackers wanting to induce an a related effect. But, if you are doing that, why not compile all virtual code native, and just leave apps with binary only Arm code sections. So Arm optimisation is not an issue But whatever they are doing in reality, as it probably is not set up this way (if only Google had insisted that all bits of binary had virtual code equivalents).

So, you just compile all virtual code to optimised arm code if you haven't got native modes. You rearrange arm binary to be more optimised if it doesn't self change. If it does self change/dynamically change, it gets complicated/slow. I know a top engineer that can show he clear benefits ofbself changing code, but from a management point of view, it is a nightmare. Unless the code change is on a native basis and preferably in an set or embedded situation, you shouldn't use self changing code.

Next to be able to pass unoptimum segments of code to the Arm cores. I forget what I read, but I think it says that they are doing this.

Anyway, load balancing is vital, you load up the CPU's with code that suites them at some point. You may start with the lower energy solution and keep loading up even if it has a performance penalty on the new code, just because ramping up another core will consume more power, until you reach a stage where it is better to ramp it up. But the issue is that ramping it up produces a power spike as the previous code is on the old core, and transferring (depending on the memory system and on chip scratch memory movement) takes some time and energy. So there has to be equations for this to maximise performance, but if you are being slack you don't bother too much (could be complex how long is a price of strong performance gain issues). So the Denver 2 seems good at both low energy and performance, so you just leave the arms to last, or if you have unoptimisable code. A lot of the time you don't need more than one or two cores anyway. One article was saying they never saw the secondary batch of cores being used on one of the Chips (can't remember which one).

So yes, there might be circumstances where an emulated core may not reach performance, but with propper management (not saying the Denver 2 is set up this way) and can produce negligent losses. I can't remember more.

Note: that the TX1 was suppose to feature a Denver 2, which was dropped. I imagine they have been spending the extra time refining the issues mentioned, and noticed in Xavier, they are going fully custom, so maybe they think it will be a thing of the past (or are they going native as well).

The parrallel computing issue. There is a comment on page about through put of 8 cores being 3x that of a single core. Which just goes to prove that you have to carefully code to maximise performance. I get that from the sega Saturn, nearly 20 years ago. They poo pooed the performance of their twin CPU's, until people started coding it better and got close to maximum performance.

 

[Wayne Morellini]

Well, that's good Antony. I remember the reaction I got years ago to wanting to buy a PC case with a sub woofer (there was one) or installed my own. The directinsl beam is around 3 decades old, and the cross ulransonic beam a bit newer, but we are talking about doing base right through the frequency range here. I think I would much rather that. Just imaging a case design to get around the omni directional sound issue now, hower it defeats the fudality purpose. You aim the sound back at a shaped surface on the case from a protrusion on the case with the drivers, aimimg to produce the sound on the surface, or as close as possible, which deflects it back in an arc, or course this is going to reduce sound quality. But that's the best I can do at half past three in the morning.

A bigger trash can could have the under subwoofer, but I want them to put an optical drive there

 

[Wayne Morellini]

This drew my attention on the Riscv membership page:

http://www.minimaprocessor.com

20x less energy usage on techniques that sound like something I would try. Factor that into large future RiscV arrays, but Apple could also use something like thus on Arm.

The first commercial RiscV product was a camera SOC believe it or not. But interesting web site:

http://www.rumbledev.com

Now, as you can get some parralelism in video encoding. Imagine using the above Minima technology to make a smaller 8k or 12k weapon with little noisy cooling. Of course Red doesn't care what I say. I would be interested in how many hundreds of MHz it can run an array at, unless it is only tens of MHz.

 

[Wayne Morellini]

Nope, just realised a limitation that may reduce the planck level performance, but may not, we don't know enough about the planck level. But it is still likely ahead of my previous proposal for planck level.

OK, theoretically the planck scale could be infinite, but how do you drive and control it? It just gets spooky past there, according to the scientific theories I'm working on.

 

[Antony Newman]

IBM

To get Intel to lower their prices of their more powerful (server) CPUs, requires a company that buys them in bulk to threaten to switch to alternative sources. By Google using an intermediate compilation point, they demonstrated they are x86, ARM and Power agnostic.

This was not enough for Intel to lower their prices, as despite Googles collosal Server inventory, there has not been a SOC that was (FLOPS) powerful enough to replace their Intel chips, and without expending far more wattage. Consequently, Intel merely offered Google a better 'matched' x86 for Googles needs.

IBMs move into the 'open' space has allowed Google to fine tune their Power code compilation, and experiment in a project to create an affordable + 'Powerful replacement for their Intel server chips. It is Intels turn to respond at this point. It would not surprise me if Intel ONLY reduced the price of their chips for Google (as no other company is in this same position).

MacOS

With Intels highest performing 12 core XEONs more of less hitting a brick wall in what they can do, and Apples Kernel limit of 12 cores - there is going to have to be some big changes (and tuning) to make use of more cores in MacOs, especially if performance penalties on the existing lineup are to be avoided.

If you were Apple, how many cores would you support? 44? Only for Intel to release a 50 core the following year? Or 64 with the Option of supporting higher core x86 Xeons and any home grown design with even more cores?

AJ

 

[Wayne Morellini]

Google is one of the members of RiscV. Being an open standard using them would mean great support for an open standard.

Power PC, nice to see them around doing this.

Intel Phi seems to be moving architecture in future towards what you are talking about.