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  • Hey all, just changed over the backend after 15 years I figured time to give it a bit of an update, its probably gonna be a bit weird for most of you and i am sure there is a few bugs to work out but it should kinda work the same as before... hopefully :)

ASIC issue...

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Oh no... :(

I feel the terrible psychological effects of the waiting :(

But wait...we have the REDONE in the meanwhile...which is fabulous :)

Thanks again to all the team for the incredible work, dedicated efforts and products... and support.

No worry, my money for the Epic is patiently waiting too.

Antoine
 
This doesn't really change anything. I mean, I didn't know when the camera I'm getting (fixed Scarlet) 1was coming out in the first place. Moving this 'non-existing' date by 30 days just moves it to another 'non-existing' date. As long as it doesn't move to far away from summer '10 it doesn't change a lot for me... So as other people have stated, just more time to save money for the camera. Thanks for the screencapture :)
 
Having been in chip design for > 10 years myself, everyone should realize that FPGA and ASIC design are nothing like one another. It's two different ball games altogether. Different challenges, and more importantly, with ASIC, performance is going to be MUCH higher.

Jim, were you all able to FIB any of the parts to test the metal changes you are making?

Most of the time, metal changes are indicative of either a logic bug OR a library characterization problem from the library vendor, but there are cases where you can test the change beforehand (not always though, depends on congestion).

Just curious, if you don't mind sharing, what technology node are you using? (45nm?)

And given the complexity you speak of, that is awesome that you got all the issues worked out in one spin. For extremely complicated designs (and I have worked on many) it's hard for the RTL designers to simulate every aspect with back annotated data.
 
From Wiki: "For most ASIC manufacturers, this consists of from two to as many as five metal layers, each metal layer running parallel to the one below it."

So, you had to go all the way to 30? Show off!!! :)

Will just have to use my fantastical, time machine delivered RED One until you get it just "RIGHT".

Thanks for all you guys are doing!

(I want an amplifier that goes to 11!) Rock On!
 
Rick Burnett said:
Having been in chip design for > 10 years myself, everyone should realize that FPGA and ASIC design are nothing like one another. It's two different ball games altogether. Different challenges, and more importantly, with ASIC, performance is going to be MUCH higher.

Jim, were you all able to FIB any of the parts to test the metal changes you are making?

Most of the time, metal changes are indicative of either a logic bug OR a library characterization problem from the library vendor, but there are cases where you can test the change beforehand (not always though, depends on congestion).

Just curious, if you don't mind sharing, what technology node are you using? (45nm?)

And given the complexity you speak of, that is awesome that you got all the issues worked out in one spin. For extremely complicated designs (and I have worked on many) it's hard for the RTL designers to simulate every aspect with back annotated data.
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Man, talks like that make me feel so small but once again remind how we were all created with various strengths and weaknesses. I don't know a thing about ASIC's except that there is one particularly that is being comprised of 30 layers and that it's development looks like it's been pushed back "only" 30 days.

I speak rEd not r&d, so I have nothing to complain about.

Half the fun has been waiting, watching, and listening to the RED team speak of their trials and achievements.

Good luck on the rest of R&D. :emote_popcorn:
 
Much love and support, Jim.

-Thor
 
Don't beat yourself up too much over this Jim. At least you're being upfront and honest with us about this, and I really respect that.

Can't wait for the beans you can spill on the 30th. :biggrin:
 
ASIC = Application Specific Integrated Circuit. It means the entire design is for a specific purpose, as opposed to say an ARM processor or anything designed to be generic and work in a multitude of applications.

Also, when it's 30+ layers, not all those are metal layers. For most of today's designs, that usually maxes out around 10 (with the top few layers being very thick). I don't know where that WIKI article came from, but most layers that are adjacent to one another are perpendicular and NOT parallel. This is due to the design of automatic routing and how each layer has a preferred direction, it would not make sense to have two directions the same over one another.

The biggest reason a metal only spin is MUCH better, other than mask costs for the whole set, is that any die's in production can be held to just below where the metal is being changed. Therefore, a whole respin of the die is not necessary and that when the new masks are ready, the process can start from that point with existing stock.
 
Jannard said:
But in the end, we will be judged by what we put out, not how long it took.
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Very true - and "A stitch in time saves nine". Its infinitely better to perfect the ASIC now - than to rush out a slightly flawed ASIC and suffer through the pain and expense of a recall. Wisdom dictates to take the time on the front end to get everything right - and I must say I'm not the least bit surprised that's your strategy. Thanks for the transparency - its a breath of fresh air in this industry.

On the added Record button, good move adding it in - and putting it where a record button has been on pro-level EFP/ENG camcorder systems for decades - on the front of the camera where its easily left-hand accessible to the operator.

Its all good Jim and RED Team - 100% happiness here :)
 
I don't think Mr. Jannard needs to be worried about any of the folks here at reduser.net wrt this delay. I do however think he should be at least slightly worried what this delay will do to RED wrt to competing products coming in 2010 from companies like Arri.

Personally, I don't mind the delay one bit. I should have my brand spanking new R1 before the end of the year and I'm more than happy to use the time between now and release of EPIC S35 learning the ropes.
 
Steve Gibby said:
Very true - and "A stitch in time saves nine". Its infinitely better to perfect the ASIC now - than to rush out a slightly flawed ASIC and suffer through the pain and expense of a recall. Wisdom dictates to take the time on the front end to get everything right - and I must say I'm not the least bit surprised that's your strategy. Thanks for the transparency - its a breath of fresh air in this industry.
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It's not the delay that bothers me, it's the sheer complexity of the ASIC design. I really hope that it's not a matter of fixing one flaw, only to have several more crop up. I have faith in Red, but this is relatively new territory for them (i.e., ASIC design of this complexity). Keeping my fingers crossed.
 
Jannard said:
BTW... this is the Side Module Upgrade. We have added a run/stop button and user settings buttons to the module. It is shown on Scarlet 8X fixed, but is the same for any brain.

Jim

Are those "brass" fittings at the front for mounting support rods?

And can I buy a mockup so my hands have something to caress until the real deal is available? :yesnod:
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