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ASIC vs. FPGA

Justin O'Neill

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I have had a lot of people ask me what exactly these ASICs are that are holding up the delivery of Scarlet and Epic. I decided to put a short post on my website giving a brief description of what they are.

I knew nothing about ASICs before hearing they were being used in the DSMC but I have been trying to brush up on the technology. If anyone has any suggestions or corrections for this post please let me know!

http://camerarentalz.com/dsmc-asic-vs-fpga/

Jim Jannard as been talking a lot lately about how important a successful spin of the ASICs for the DSMC is to the Scarlet and Epic ship date so we thought we would give a brief overview of what exactly he means.

ASIC stands for Application-Specific Integrated Circuit and is basically the “system on a chip” that will run the Scarlet and Epic brains. The reason we haven’t heard of these before is the RED One camera uses an FPGA or Field-Programmable Gate Array. The differences between the two systems are listed below:

FPGA

FPGA hardware is re-programmable via software. This doesn’t mean you can turn your RED One into a laser (not 100% sure on this) but it has allowed RED to add features that weren’t in the original design, such as ramping, 2k @120FPS, Color Science, etc. The ability to re-program also means a much quicker development time as features can be enabled and bugs fixed with software updates once the hardware is out in the field. FPGAs are closer to actual computers and have components like memory and CPUs which must be booted up in sequence (thus the long boot up time on the RED One).

Pros:

* Re-programmable
* Much quicker development time

Cons:

* Slower
* Slow power up
* Runs hot
* Large
* Power hungry

ASIC

ASICs are mainly controlled by hardware chips and are designed for a specific job. Small firmware updates can be made but nothing near what is possible on the RED One. This means development can take much longer as features have to be built into the chips and bugs squashed prior to shipping. Due to the hardware being optimized for a singular purpose, ASICs are small, very fast and run cool. Most consumer electronics like cellphones and cameras are controlled by ASICs these days and we can expect a start up time closer to DSLRs for the DSMC. Hardware optimization also means the DSMC will be much less power hungry and from the look of it will be able to use much smaller batteries.

Pros:

* Fast
* 1-2 second start up
* Runs cool
* Small
* Power efficient
* Cheaper in large quantities

Cons:

* Can’t add features
* Longer development time
 
I have had a lot of people ask me what exactly these ASICs are that are holding up the delivery of Scarlet and Epic. I decided to put a short post on my website giving a brief description of what they are.

I knew nothing about ASICs before hearing they were being used in the DSMC but I have been trying to brush up on the technology. If anyone has any suggestions or corrections for this post please let me know!

http://camerarentalz.com/dsmc-asic-vs-fpga/

Thanks for posting this Justin... but Jim also stated CLEARLY

that these cameras are not 100% ASIC cameras... that is one element
but it is a HYBRID Camera System of ASIC and FPGA is my guess.

A little bit if info can lead to dangerous assumptions. Of course we can upgrade the firmware on EPIC & Scarlet. Never said we ONLY had an ASIC in there...

Jim

ASIC's are critical to their plans, but these cameras will not have the most relevant CON of ASICS... and that is... they WILL be upgradeable firmware wise.

IT is also more relevant to refer to ASICS in the DSMC context as a SOC (system on a chip) which can provide a more customized application.

I am also completely guessing here... but it is my theory that the challenges are relative to their attempts to hyrbidize this solution...

However... the "delays" are moreso relative to not wanting to ship a BETA Epic or Scarlett but to get it as right as possible before shipping. (unlike RED ONE)
 
Here's another one for you: ASICs cost millions of dollars to make the "mold" (so to speak) to make one, and then cheap to make tons of them. You make your gigantic initial costs back in the long run.

So basically if you made an ASIC and THEN discovered the bug? yeah, you're screwed, there went your millions, throw it away, tweak it, and "tool up" for the next one. So, you want to take your time and make sure you're only burning a FULLY TESTED and vetted ASIC, no room for the patended develop-as-we-go Red One FPGA style.
 
Depending on design, ASICS can be updated with firmware just like any processor chip that runs software.
An FPGA is an open architecture chip that does not have a defined circuit design. It is the hardware circuits that are reprogrammable. The hardware circuit designs are fixed in an ASIC, but software is not always fixed.
The DIGIC processors in Canons are ASICS bu they can obviously be updated with new firmware, to a point. You can't exceed the inherent limitations of the hardware.
 
My question is what does a "successful spin" refer to? What is a "spin"?
 
This doesn’t mean you can turn your RED One into a laser (not 100% sure on this) but it has allowed RED to add features that weren’t in the original design, such as ramping, 2k @120FPS, Color Science, etc.

Color Science upgrades are in the PC side software not the camera. Also something as 'simple' as the color matrix will almost certainly be something that could be changed through firmware. It's not a terribly taxing part of the chip it's something which will almost 100% certainly change over time which means I'm sure RED has built that assumption into their architecture.
 
There are many, MANY, pieces of complex hardware that use ASICs for specific portions of the work they do.

A managable network switch, for examle, will use ASICs for the actual heavy lifting of packet-decoding and forwarding on it's many 1Gbps ethernet ports. ASICs allow it to do massive amounts of heavy computation and I/O for relativiely little cost (after initial R&D).

These are defined repeatable tasks, such as header decoding, packet transfer, checksum calculation, filter rules, etc... In the Red world this can be a debayer, RGB conversion,metadata application etc...

However, those switches ALSO have a CPU that runs an OS, which coordinates the activity of all the ASICs as well as handles other parts of functionality such as port assignment, logging, performance gathering, etc... A firmware/OS update for a switch can add completely new functionality, or change existing functionality.

In the Red world, it's likely that such upgrades will continue to give us new and refined features. It's simply that the grunt work will be handled by these special-purpose chips that are smaller/faster/cooler/less power hungry than using an FPGA for the task.

Look at it this way: the RedRocket is in essence a ginormous ASIC that knows how to Debayer to RGB. Yet RocketCINE can be (and has been) updated to add new features, and change the way it "directs" the Rocket to behave in performing it's dedicated task (i.e. an updated RocketCine can supply new decoding transforms to the Rocket to improve the way it handles apply color space conversion, metadata application, etc...).

As a matter of fact, if I were a betting man I'd guess that some of the silicon on the Rocket and in the Scarlet/Epic cams are at least cousins, if not twins. ;-)

-sc
 
As a matter of fact, if I were a betting man I'd guess that some of the silicon on the Rocket and in the Scarlet/Epic cams are at least cousins, if not twins. ;-)

you're right.. I never heard about RED Rocket before the announcement of the scarlet and epic.. you also may say that RED started playing with ASICs when they planning the DSMC,, made some nice debayering circuits for the developments then they found the idea of the Rocket out of their assmebled ASICs prototypes.. so, they produced it on the way..

the things that comes to my mind next is: if that is true then why they optimized the rocket for 4K while all DSMCs (except 3K scarlets) starts from 5K resolutions? maybe the rocket will be able to handle more res but for 4K output to projectors as a standard..
 
I think the decision was actually simpler...

Why offer 5K when everything at present can do 4K?

Jim's already said it can handle 5K...

Firmware update and it could do the same for 5K as it does for 4K surely...
 
you're right.. I never heard about RED Rocket™™ before the announcement of the scarlet and epic.. you also may say that RED started playing with ASICs when they planning the DSMC,, made some nice debayering circuits for the developments then they found the idea of the Rocket out of their assmebled ASICs prototypes.. so, they produced it on the way..

the things that comes to my mind next is: if that is true then why they optimized the rocket for 4K while all DSMCs (except 3K scarlets) starts from 5K resolutions? maybe the rocket will be able to handle more res but for 4K output to projectors as a standard..

As Imran referred to, 5K at limited frame rates for the current rocket has been mentioned. And it's been noted that one of the configuration files for RocketCine has a line for # of Rocket Cards detected as installed... so it may not be out of the question to gang them up for higher res processing.

-sc
 
Thanks for all the great replies!

I tried to make it clear in the post that firmware upgrades were still possible with an ASIC but maybe I underestimated the level of features that can still be added to the DSMC once it ships.

Tim, thanks for pointing out that Jim said there will be other components in the DSMC that will allow for flexibility. Here is the post for anyone who is interested:

The ASIC does lots of stuff... heavy processing with less power (heat), quick startups (less than 2 sec) but is limited to changing things around. We have added other stuff in the brain to provide flexibility. Building a complicated and powerful ASIC is not an easy task.

Jim

And another:

There are more electronics in a brain than just an ASIC. But an ASIC does remove a lot of heat generating electronics that are in a RED ONE. Firmware upgrades are still possible in the Scarlet/EPIC system.

Jim

David, thanks for the clarifications. I will try to include them without getting too technical because I am trying to make this readable for your average film producer/35mm DP.

Gavin, thanks for pointing out the Color Science issue, I have removed that example from the post.

I will be adding the point about enormous initial ASIC development costs. Thanks, Shawn.

Heading off to update the post.
 
Sounds like, (and I am guessing here) that the new ASIC system being developed will in turn lead to a more stable running camera than the previous FPGA system along with all the other mentioned benefits? Or will we still be at the mercy of the software?
Of course there are other hardware issues that can be involved in bugs/incompatibilities and inconsistencies like a drive cable issue, bent CF Module pins etc. Am I fishing here or is this fairly accurate to assume that the new cameras will be more stable from the get go because of the new system?
 
Interesting thread! Great post, Justin - good work.

3 quick things to throw into the mix:

1) I don't think we can make any predictions about EPIC / Scarlet's power consumption at this point. Yes, it seems to be the case that an ASIC will use less juice than an FPGA when performing the same task, but the EPIC and Scarlet brains are so different from the RED ONE in many ways that I don't think it's safe to make predictions about power consumption at this point.

2) As has been mentioned before, almost all "complex" modern mass-produced electronics which do large amounts of task-specific number crunching (including the Scarlet, Epic, Canon 5D mkII, GH1 etc etc) will probably use a purpose built ASIC to do the heavy lifting (debayering, REDCODE encoding etc) but will also contain a general purpose CPU (for coordinating all the other components, running the UI etc), RAM, FLASH etc. Those logical units may or may not be on a single wafer of silicon.

3) The latest Red Centre podcast suggested that the RED Rocket™ is essentially the same card as the card in the DVS Clipster and may not actually bare much relationship to the hardware in the Scarlet / Epic / RED ONE. Has anyone pulled the heatsinks off the chips on a RED Rocket™ to look at the text printed onto the chips?!? (I wouldn't recommend doing that unless you really know what you're doing! The heatsinks may be glued onto the chips).
 
Sounds like, (and I am guessing here) that the new ASIC system being developed will in turn lead to a more stable running camera than the previous FPGA system along with all the other mentioned benefits?

I think the DSMC will be more stable because RED will be able to incorporate everything they have learned with the RED One.

I don't know think ASICs themselves are inherently more stable then FPGAs.
 
No need for that. The cards look almost identical (comparison images on here) and I seem to remember RED acknowledging DVS for help with aspects of it.

DVS do OEM work, so it's not surprising RED turned to them to produce the card. In no way should anyone see this as some kind of cop-out or negative. RED and DVS make some great gear, so its fantastic that they are working together.
 
No need for that. The cards look almost identical (comparison images on here) and I seem to remember RED acknowledging DVS for help with aspects of it.

DVS do OEM work, so it's not surprising RED turned to them to produce the card. In no way should anyone see this as some kind of cop-out or negative. RED and DVS make some great gear, so its fantastic that they are working together.

I've seen a report that the Rocket has "DVS" silkscreened on it.

While I'm sure that the packaging for the silicon on the Rocket is likely differerent, I suspect that much of the R&D for the silicon in the Rocket will be directly applicable to the modular cams... they have similar requirements for a number of their pipeline steps.

Or it could be completely seperate IP that DVS retains rights to...

-sc
 
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