Sergio Perez
Well-known member
Haven't gone through all the posts so sorry all if this was already posted, but where can I find this Pixar demonstration and talk with the new Macpro?
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: this_feature_currently_requires_accessing_site_using_safari
For as long as you will keep making these hasty comments without putting things in perspective - you are bound to get responses like mine. I would like to see the "cheap gaming PC" you have mentioned to open up that 30GB texture set in Mari and work on it while being able to play the scene animation and see instant feedback, including all the image channels (such as bumb, specular, etc...)...
But don't take my word for it - the guys from Weta and Pixar that made that presentation are facing daily challenges that 99% of us would never do. And they clearly have stated that Mari has never run smoother with such a set of data.
IMO, cloud is a 4-letter word...
Haven't gone through all the posts so sorry all if this was already posted, but where can I find this Pixar demonstration and talk with the new Macpro?
Yes. But there are two of those 20Gbps pipelines in each Thunderbolt port. Thunderbolt 2 also allows channels and even ports to be multiplexed for increased capabilities. Two Thunderbolt 2 ports multiplexed together has about the same throughput as a PCIe v2 X16 slot. Higher latency, of course, but still close to the same bandwidth. Each Thunderbolt 2 port is backed by 4 lanes of PCIe v3 at 985MB/s per lane. That's 3.9GB/s and real-world throughput is closer to 3.5GB/s, plus some overhead for the Thunderbolt host and whatnot. I don't think it's unreasonable to expect 3GB/s+ out of a TB2 port.
The real trick to all this is what devices will actually come to the table. The unfortunate side of this is that very few users, and even fewer devices, are going to need any of those multiplexing abilities or huge bandwidth. So I fear that we may not see some of these faster expansion chassis or mega-speed storage options that are possible. If we do, they will likely be niche products and rather expensive. Time will tell.
I don't think you are correct here. First, Thunderbolt 2 is not PCIe 3.0. Its still PCIe 2.0. Secondly, there is only one 20 Gb/s channel in the Thunderbolt 2.0 specification, it is simply bi-directional (this is why there are two channels shown in the Intel diagram, one is upstream and one is downstream). So max theoretical bandwidth is nowhere closer 3.9 GB/s per port. With overhead from 8b/10b, you're looking at closer to 16 Gb/s peak performance, which is 2 GB/s.
It follows, then that two TB ports are lucky to get half the real world performance of a x16 PCIe 2.0 slot.
In your analysis you cite overhead and note the "real world" performance of a bus vs the theoretical spec when evaluating TB2, but not for PCIe? I certainly don't have all the answers, shipping TB2 devices, both host and peripherals, are at the very least 3 months away. Not to mention we lack metrics on efficiency ratios when multiplexing the ports. If your goal is to defend the value of PCI card architecture, then I don't doubt its maturity vs TB gives it the short term advantage.
My counter would be that in a world of 22nm process chips, the form factor of the PCI bus requires more power, cooling and physical space than makes sense going forward. Only time will tell if Apple and TB2 will provide the necessary muscle for the "big data" future, but with nano tech on the doorstep I see PCIe as a dead man walking.
Cheers - #19
I personally miss the days of buying a tool that lasted for quite some time. I have been trying to justify purchases more these days. But for me the whole reason of the Mac Pro being useful was the PCI expandability. Without it, I might as well buy a more mobile solution...
As I understand it, the 500 MB/s figure for PCIe 2.0 includes encoding overhead. Which is why when you calculate the bandwidth of TB (4 lanes of PCIe 2.0), you get 2GB/s, which is 16 Gb/s, not 20 Gb/s.
I'm not trying to claim superiority of one standard over the other, just clarifying the facts. They are both different, and have different places as far as I'm concerned (although TB will probably replace PCIe in the long run). TB is hot swappable, carries display signal, can be connected via longer distances, but PCIe simply has higher bandwidth at this point. It is just a trade-off.
I don't think you are correct here. First, Thunderbolt 2 is not PCIe 3.0. Its still PCIe 2.0. Secondly, there is only one 20 Gb/s channel in the Thunderbolt 2.0 specification, it is simply bi-directional (this is why there are two channels shown in the Intel diagram, one is upstream and one is downstream). So max theoretical bandwidth is nowhere closer 3.9 GB/s per port. With overhead from 8b/10b, you're looking at closer to 16 Gb/s peak performance, which is 2 GB/s.
It follows, then that two TB ports are lucky to get half the real world performance of a x16 PCIe 2.0 slot.
That's pretty much correct in terms of PCIe 2.0 bandwidth. It's 500MB/s per lane, or 2000MB/s for an X4 host. Which is what drives Thunderbolt 1.0. With the 10bit/byte overhead, we get 1600MB/s or 16Gbps backing each Thunderbolt 1.0 port.
Thunderbolt 2 PCIe topology is still indeed based on PCIe 2.0. However, the Falcon Ridge controller is backed by PCIe v3. So I guess you could say that some semantics are getting in the way. I only said it was backed by PCIe 3.0, which is indeed the case.
If you want to get to the nitty gritty of Thunderbolt channels, Thunderbolt 1 has two 10Gbps channels. Thunderbolt 2 has 4 of them. By default, when the port runs in Thunderbolt 2 mode, the channels are bonded as 2 x 20Gbps channels per port. As for the upstream and downstream orientation, that is the intended operation, but in fact both channels are bi-directional capable, just as they are in Thunderbolt 1. When using a port for Displayport or video signaling, the secondary 20Gbps allocation is a one-way street, just as the secondary 10Gbps channel is when connecting a display to a Thunderbolt 1.0 host. When a display is connected to Thunderbolt 1, the secondary channel becomes video only and the primary channel has to operate in bi-directional mode. I have yet to see any complete diagram online that fully represents the operation of Thunderbolt 2, or Thunderbolt 1 for that matter.
There are several unanswered questions and some compromises along the way as well. Using Thunderbolt 1 devices on a Thunderbolt 2 port seems to cause the primary 20Gbps allocation to split into dual 10Gbps streams to accommodate the v1 topology. While all channels in a Thunderbolt port can be bi-directional, there is a significant penalty on the switching, so therefore the intended use is an upstream and downstream orientation.
Intel has released a lot of preliminary specs through their usual dev channels. I'm assimilating my info by what I'm being fed from a couple sources, trying to verify as much as I can. Full release doesn't happen for another week or three. Only their key integration partners have the info so far -- Apple, HP, ASUS... And Intel hasn't lifted the gag order just yet. Still waiting on confirmation of asynchronous matching and dynamic bandwidth allocation or load balancing of ports and other features.
Each TB2 port is backed by 4 lanes of PCIe v3, which is 985MB/s per lane for an aggregate of 3940MB/s or 3.84GB/s. Translate this with the 10bit/byte overhead and that works out to 33Gbps. When it's a "40Gbps port". So as with Thunderbolt 1, we are already seeing a port with insufficient backing to reach its advertised potential. If it holds true to the performance we've come to expect from TB1, we get about 93% nominal efficiency, so based on that, I expect a nominal throughput per port on TB2 of about 2.9GB/s... I was saying 3GB/s in my post above, but after I put some real numbers to it, it's not so rosy... Most devices are only going to see a little better than half of that as the ports will be primarily allocated as split up/ down streams with some efficiency loss.